In order to increase performance of electronic systems, integrated circuits (ICs) are being designed to handle high amounts of data traffic (large numbers of input signals, such as data and/or address values). For example, memory devices can have “wide” input/output configurations (interfaces of greater than 256 data bits). More particularly, quad data rate type static random access memories (QDR SRAMs). Such high traffic devices can dissipate significant amounts of power. Such power consumption can result in undesirably large draws in power supply current, resulting in power supply voltage fluctuations. If such fluctuations are large enough, an IC can fail or suffer damage.
To mitigate these risks, the power needs of such ICs are controlled or maintained to be near static, resulting in high levels of wasted power dissipation when the device is not accessed. This effects product competitiveness, as it is also desirable to have the lowest possible power dissipation when portions of an IC are not in use.
Across the power spectrum of an IC device, various solutions can be applied to minimize voltage drops arising from resistance (IR) and inductance L(di/dt). DC power dissipation arises from on-die power grid wires, resulting in a static IR drop. To address this static IR drop, the power and ground grid (PG pins) can be constructed with a minimized resistance and the operating circuit can be made to draw less current.
For transient characteristics, where the voltage drop is determined by I(t)R+L(di/dt), current is drawn from the power supply and from local area pre-charged capacitance. The resistance from the circuit to both the power supply and the pre-charged capacitance can be minimized to limit the I(t)R component. Often though, the primary issue for transient responses can be the L(di/dt) component, as current passes through the inductive, external power connections to the device. To prevent high frequency current from passing through the PG pins, decoupling capacitors are used. Decoupling capacitors can act to bypass or “decouple” the external power supply connection from the circuit being served. They can translate high frequency circuit current draw to lower frequency current that passes through the external connections.
FIG. 24 is a graph showing a current draw I(f) of an IC versus frequency. Included is current draw arising at pins 2455 as well as that resulting from circuits 2457. FIG. 24 also shows an impedance of an IC power distribution network (Z_PDN(f)) versus frequency. A current draw of an IC can have very high frequency components yet the current through the PG pins reaches a lower maximum frequency.
Once the current passes through the PG pins, the external power delivery network (PDN) characteristic (2461) becomes dominant. An external PDN is typically designed to address low frequency current, where larger decoupling capacitors (2465) exist at the package and board levels to address high frequency current
One way to ensure current draw does not adversely affect or damage a high traffic IC is to limit the number of active data paths. As but one particular example, in a wide I/O memory device with multiple independent channels, there can be limit to the number of channels allowed to access the memory arrays at the same time.
Power dissipation in a high data traffic IC can also be data pattern dependent. The more data states change, the more power is consumed. As but one very particular example, different data patterns for a QDR wide I/O SRAM are considered. These cases are estimates, and provided only to understand data pattern power dependence. In a first case, in a 32 channel read operation from memory for more than 10 cycles, where all data signals do not change state, a maximum power level under this condition is estimated to be about 9W. In contrast, in a second case, if the same device is undergoing 16 channel read operation from a data cache (cached write data) for more than 10 cycles, where all data signals are toggling, and a 16 channel WRITE to data cache, where all data signals are toggling, an estimated maximum power level can be about 15W.
The number of cycles it takes to transition from the first state to the second state can be 4 cycles. Using 4 cycles as the ramp time, the maximum di/dt in this ramp time is estimated to be roughly 1.2 to 1.3 A/ns, which cannot be supported by many conventional PDNs. Further, in this scenario, the result can potentially be a 6A change in current between the two states. If this cycle repeats at a rate near of 30-80 MHz (13-30 ns), a worst case power supply oscillation can result if the frequency coincides with the power delivery network's (PDN's) resonance frequency.
One way to reduce di/dt can be a return-to-common signaling for data lines. Such a solution can be costly in area required, however, as it requires two wires per signal and a control circuit to control the switching.